Post-silicon is too late avoiding the $50 million paperweight starts with validated designs
- Year
- 2010
- Authors
- John Goodenough, Rob Aitken
- DOI
- 10.1145/1837274.1837279
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Persistent Notes
In-text annotations
“Silicon-proven IP is always desirable, but to be effective, silicon validation must be preceded by careful design validation. A primary reason for this is time: if a problem is found in silicon that requires redesign and a silicon respin, six months to a year will be lost in IP delivery , typically including 1-4 months to make changes to the design and find another silicon shuttle, another 3-5 months in the fab (longer for new processes), and another 1-2 months to validate the new silicon when it is delivered. On the other hand, a problem found in emulation can be identified, debugged and fixed in days. Timing errors found after place and route can usually be fixed quickly with an ECO flow, and even bugs that require resynthesis add perhaps a few weeks to a schedule. Given the highly time-sensitive nature of the semiconductor industry, waiting for silicon to check for problems is clearly a failing economic approach, even before considering the expense associated with test silicon." Page 8
Pre vs Post verification and why post-silicon verification is too slow. Page 8
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