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Lecture 2

Questions

  • In a Harvard architecture, where is the data stored?
    • RAM
  • In a Harvard architecture, where is the instructions stored?
    • ROM
    • Instructions cannot be modified. Ergo Read-only
  • Draw the bus diagram of an ARM Cortex-M system
  • What are the different buses in an ARM Cortex-M system
    • Icode
    • Dcode
    • System Bus
    • Private Peripheral bus
    • Advanced High Performance Bus
  • How many stages are there in ARM Cortex-M?
    • 3
  • Comment on the order of execution?
    • Inorder
  • What are the size of RAM and ROM in TM4C123
    • 32K RAM
    • 256K ROM
  • Give the MMIO memory map
    • ROM
    • RAM
    • I/O
    • Internal I/O and PPB
  • What is the granularity of the memory model?
    • Byte addressable
  • What is the alignment of data?
    • Word aligned 32-bit 4-byte
  • What does it mean for the data to be word aligned?
    • The CPU access 32-bits at once
    • Each read/write will be 32-bits
    • Hence the data is aligned in such a way to make this possible
    • Even if you try to read 8-bits in the middle the system has to read the 32-bit that surrounds the target
  • Assume that some data read is not word aligned what would happen?
    • If the data to be read is somehow not word aligned then multiple reads have to be done.
  • What is a fast trick of identifying invalid data address
    • Due to this word alignment we know that the blocks are all multiple of 4
    • So the LSB goes 0, 4, 8, C
    • 1, 2, 3 and their counterpart are “inside” the block
  • What is bit banding?
    • Accessing individual bits
  • What does Big-Endian and Little endian mean?
    • The lower address has the Big(MSB) or the little(LSB) end
    • Suppose the data is 0x12345678
    • Big endian will store it as 0x12345678
    • Little endian will store it as 0x87654321
  • How would you store the string "hello, world" in big endian vs little endian?
    • Strings are stored in the same order as they are declared
  • What property of strings makes it so that there is no difference in the storage layout ?
    • The offsets have a distinct meaning with dealing with strings
    • With ints we don’t really chop them up into bytes. If all we are doing is reading them as a whole we can be opaque to how they are represented in memory
    • char is just a byte. We often read between the block and the semantics will be different if we changed the order
  • Assume a 32-bit integer is stored in memory what would be the results of reading at half and byte addresses in big endian vs little endian
    • We would have very different results
  • What are the registers in ARM Cortex-M
    • R0 to R15
    • R0 to R12 are general purpose registers
    • R13 is the stack pointer. It is a banked register and has two versions MSP and PSP
    • R14 is the Link register
    • R15 is the PC
  • What are the registers used for function calls?
    • R0 to R3 are used to send args
    • R0 is used for returns
  • Where are MSP and PSP located?
    • They are the same. They are banked
  • What are the initial values of the register when reset is asserted?
    • SP is to ROM[0]
    • LR is set to 0xFFFF.FFFF
    • PC is set to the value at ROM[4]
  • What mode does the CPU start in?
    • Privileged mode
  • What is the LSB of all instructions and why?
    • 0
    • 16 bit or 32 bits
    • 16 bit would be 00 or 01
    • 32 bit would be 00
  • What is LSB[0:2] look like for stack accesses and why?
    • Since stack access are word aligned, they always end with two 0s
  • When an item is pushed onto the stack, what happens to the SP?
    • It is decremented.
    • In ARM, stack grows “down”
  • What is AAPCS?
    • ARM architecture Procedure Call Standard
  • What registers are used to pass arguments to a function?
    • R0-R3
  • Where is the return data present?
    • R0
  • What are the registers that needs to be saved
    • R4-R11 needs to be saved
  • Why not save R12?
    • R12 is linkers scratch register. No need to save it
  • What is the required alignment of the stack?
    • Stack should be 64-bit algined
  • What are the rules for pushing/popping onto the stack?
    • Push/pop in even multiples of 8
  • What is the rationale behind those rules?
    • First of all, AAPCS dictates this
    • 32-bit systems might have 64 bit floats.
    • Hence a since call should be able to retrieve this.
  • What are the two clock sources in TM4C
    • MOSC - Main Oscillator
    • PIOSC - Precision Internal Oscillator
  • What allows for adjusting the frequency?
    • Phase Lock Loop
  • What is the range of TM4C clock configurations?
    • 3.25 Hz to 80MHz
  • What are the registers used to control the SysClk?
    • RCC and RCC2