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svabench Implementation notes

Dataset selection

  • I have no clue about what is happening in pulavarthiAssertionBenchBenchmarkEvaluate2025 repo
  • There are so many designs. I don’t know if we need all of those. I get the rationale for having loads of designs but not all the designs are created equal. We need good data for the LLMs. I obviously cannot manually check the “goodness” of each of the design. I am just going to use opencores’s certification as my goodness indicator.
  • They were manually checked by the folks there. So there was some human involved in the loop
  • This is the entire list https://opencores.org/projects?language=Verilog&certifiedProject=true
  • In total there are 19 designs

Structure

  • I have to convert all of the files into sva_bench style folders. Just have all the rtl files under rtl/.
  • Possibly do verification on single modules