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2026-02-17 Meeting

What I did?

  • Refactor many parts of pyverilog and ply
    • Some parts are not well written
    • They are still inheriting from Object
    • No support of systemverilog. May need one in the future if the assertions are syntactically wrong
      • But rn they seem fine
  • Claude Code results on apbi2c
Module Proven Total Cover %
fifo 27 27 100
apb 22 22 100
module_i2c 31 32 93%
i2c 19 19 94%

Quirks

  • Ran many commands by itself
    • ls, grep, head
  • It didn’t know that .tcl files don’t support env expansion
  • fifo.v errored out because it had a combinatorial loop, so I had to create a latch in-between
  • Each file took approximately 5 minutes
  • Has no idea about jasper gold
    • Created loop_cut command out of thin air
  • It automatically compacted my context window after the third file
  • This was all done without a CLAUDE.md file. Idk how much it will help but I just read paper concluding that it actually negatively affects performance across the standard LLM SWE benchmarks

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