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Project Ideas
- Implications of the non-inclusion of division , multiplication and loop operation in SDN
- Using lightweight AI inference on P4 switches to determine routing and load balancing.
- Separated ECN: sending back a special metadata package to indicate congestion the first time a packet encounters congestion to provide quicker feedback to devices.
- Using optical circuit switching to enable dynamically-changing network topologies for changing workloads.
- Investigating the host network of an ARM server with more open/available documentation about its architecture so that we can verify our results.
- Pi-Hole like DNS level blocking using P4
- Rate limiting at the switch level
- TOR vulnerabilities https://www.usenix.org/system/files/conference/usenixsecurity15/sec15-paper-sun.pdf
- ML inference in the data plane https://eng.ox.ac.uk/media/zetja3ek/zheng24planter.pdf
Slide Notes
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A host can be modeled as a network of CPUs, Memory and Peripherals
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Congestion in these links can have far reaching consequences
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breaks the conventional wisdom that congestion occurs on the network fabric. But network bandwidth has exploded to the point that the interconnects inside the host may be the bottleneck
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Raspberry Pi
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DDIO from intel is not available
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Different uncore perf setup
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Will the RIO controller be a bottleneck
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What about peripherals to ethernet? (Video streaming)